 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Presettable 4-Bit Down Counters The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS P-channel and N-channel enhancement mode devices in a monolithic structure. These devices are presettable, cascadable, synchronous down counters with a decoded "0" state output for divide-by-N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide-by-N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. These complementary MOS counters can be used in frequency synthesizers, phase-locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Logic Edge-Clocked Design -- Incremented on Positive Transition of Clock or Negative Transition of Inhibit * Asynchronous Preset Enable * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value MC14522B MC14526B L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII Unit V V - 0.5 to + 18.0 10 500 - 65 to + 150 260 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8-Second Soldering) mA mW ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = - 55 to 125C for all packages. PIN ASSIGNMENT Q3 P3 PE INHIBIT P0 CLOCK Q0 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q2 P2 CF "0" P1 RESET Q1 _C _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C FUNCTION TABLE Inputs Clock X X X X L H H Reset H H H L L L L L L L Inhibit X X X X H L L Preset Enable L H X H L L L L L L Cascade Feedback L L H X X X L L L L Output "0" L H H L L L L L L L Resulting Function Asynchronous reset* Asynchronous reset Asynchronous reset Asynchronous preset Decrement inhibited Decrement inhibited No change** (inactive edge) No change** (inactive edge) Decrement** Decrement** This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v X = Don't Care NOTES: * Output "0" is low when reset goes high only it PE and CF are low. ** Output "0" is high when reset is low, only if CF is high and count is 0000. REV 3 1/94 (c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14522B MC14526B 1 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Sink Iin Cin IDD Adc pF Adc IT IT = (1.7 A/kHz) f + IDD IT = (3.4 A/kHz) f + IDD IT = (5.1 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. MC14522B MC14526B 2 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Symbol VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns tTLH, tTHL (Figures 4, 5) Propagation Delay Time (Inhibit Used as Negative Edge Clock) Clock or Inhibit to Q tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns Clock or Inhibit to "0" tPLH, tPHL = (1.7 ns/pF) CL + 155 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Propagation Delay Time Pn to Q Propagation Delay Time Reset to Q Propagation Delay Time Preset Enable to "0" Clock or Inhibit Pulse Width tPLH, tPHL (Figures 4, 7) tPHL (Figure 8) tPHL, tPLH (Figures 4, 9) tw (Figures 5, 6) Clock Pulse Frequency (with PE = low) fmax (Figures 4, 5, 6) Clock or Inhibit Rise and Fall Time tr, tf (Figures 5, 6) tsu (Figure 10) Hold Time Preset Enable to Pn Preset Enable Pulse Width th (Figure 10) tw (Figure 10) Reset Pulse Width tw (Figure 8) Reset Removal Time trem (Figure 8) tPLH, tPHL (Figures 4, 5, 6) 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 100 80 -- -- -- -- -- -- 90 50 40 30 30 30 250 100 80 350 250 200 10 20 30 550 225 160 240 130 100 260 120 100 250 110 80 220 100 80 125 50 40 2.0 5.0 6.6 -- -- -- 40 15 10 - 15 -5 0 125 50 40 175 125 100 - 110 - 30 - 20 1100 450 320 480 260 200 520 240 200 500 220 160 440 200 160 -- -- -- 1.5 3.0 4.0 15 5 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns MHz s Setup Time Pn to Preset Enable ns ns ns ns ns * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. MOTOROLA CMOS LOGIC DATA MC14522B MC14526B 3 VOH VDD = -VGS CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 "0" EXTERNAL POWER SUPPLY IOH VOL VDD = VGS CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 "0" EXTERNAL POWER SUPPLY IOL VSS VSS Figure 1. Typical Output Source Characteristics Test Circuit Figure 2. Typical Output Sink Characteristics Test Circuit VDD CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 Q3 "0" VSS CL PULSE GENERATOR CL CL DEVICE UNDER TEST CL CL Q or "0" CL* TEST POINT 20 ns CLOCK 20 ns VDD 90% 50% 10% VSS VARIABLE 50% DUTY CYCLE WIDTH * Includes all probe and jig capacitance. Figure 3. Power Dissipation Figure 4. Test Circuit MC14522B MC14526B 4 MOTOROLA CMOS LOGIC DATA SWITCHING WAVEFORMS tr CLOCK 90% 50% 10% tw 1/fmax tPLH ANY Q OR "0" 90% 50% 10% tTLH tTHL tPHL ANY Q OR "0" 90% 50% 10% tTLH tTHL tPLH tf VDD INHIBIT VSS tf 90% 50% 10% tw 1/fmax tPHL tr VDD VSS Figure 5. Figure 6. tw VDD RESET tr ANY P 90% 50% 10% tPLH ANY Q tPHL trem 50% CLOCK VDD 50% VSS tf VDD VSS ANY Q 50% VSS tPHL 50% Figure 7. Figure 8. VALID tr PRESET ENABLE 90% 50% 10% tPHL tPLH PRESET ENABLE "0" 50% tw 50% VSS tf VDD GND ANY P 50% VSS tsu th VDD VDD Figure 9. Figure 10. MOTOROLA CMOS LOGIC DATA MC14522B MC14526B 5 PIN DESCRIPTIONS Preset Enable (Pin 3) -- If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3. Inhibit (Pin 4) -- A high level on the Inhibit input pre- vents the Clock from decrementing the counter. With Clock (pin 6) held high, Inhibit may be used as a negative edge clock input. Clock (Pin 6) -- The counter decrements by one for each rising edge of Clock. See the Function Table for level requirements on the other inputs. Reset (Pin 10) -- A high level on Reset asynchronously forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is high, causes the "0" output to go high. "0" (Pin 12) -- The "0" (Zero) output issues a pulse one clock period wide when the counter reaches terminal count (Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and Preset Enable is low. When presetting the counter to a value other than all zeroes, the "0" output is valid after the rising edge of Preset Enable (when Cascade Feedback is high). See the Function Table. Cascade Feedback (Pin 13) -- If the Cascade Feedback input is high, a high level is generated at the "0" output when the count is all zeroes. If Cascade Feedback is low, the "0" output depends on the Preset Enable input level. See the Function Table. P0, P1, P2, P3 (Pins 5, 11, 14, 2) -- These are the preset data inputs. P0 is the LSB. Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) -- These are the synchronous counter outputs. Q0 is the LSB. VSS (Pin 8) -- The most negative power supply potential. This pin is usually ground. VDD (Pin 16) -- The most positive power supply potential. VDD may range from 3 to 18 V with respect to VSS. STATE DIAGRAMS MC14522B 0 1 2 3 4 0 1 MC14526B 2 3 4 15 5 15 5 14 6 14 6 13 7 13 7 12 11 10 9 8 12 11 10 9 8 MC14522B MC14526B 6 MOTOROLA CMOS LOGIC DATA MC14522B LOGIC DIAGRAM (BCD Down Counter) P0 5 Q0 7 P1 11 Q1 9 P2 14 Q2 15 P3 2 Q3 1 DR C T PE Q VSS D RQ C T PE Q D RQ C T PE Q D RQ C T PE Q CF PE INHIBIT 13 3 4 12 "0" CLOCK RESET 10 6 MC14526B LOGIC DIAGRAM (Binary Down Counter) P0 5 Q0 7 P1 11 Q1 9 P2 14 Q2 15 P3 2 Q3 1 DR C T PE Q VDD D RQ C T PE Q VDD D RQ C T PE Q D RQ C T PE Q CF PE INHIBIT 13 3 4 12 "0" CLOCK RESET 10 6 MOTOROLA CMOS LOGIC DATA MC14522B MC14526B 7 APPLICATIONS INFORMATION Divide-By-N, Single Stage Figure 11 shows a single stage divide-by-N application. The MC14522B (BCD version) can accept a number greater than 9 and count down in binary fashion. Hence, the BCD and binary single stage divide-by-N counters (as shown in Figure 11) function the same. To initialize counting a number, N is set on the parallel inputs (P0, P1, P2, and P3) and reset is taken high asynchronously. A zero is forced into the master and slave of each bit and, at the same time, the "0" output goes high. Because Preset Enable is tied to the "0" output, preset is enabled. Reset must be released while the Clock is high so the slaves of each bit may receive N before the Clock goes low. When the Clock goes low and Reset is low, the "0" output goes low (if P0 through P3 are unequal to zero). The counter downcounts with each rising edge of the Clock. When the counter reaches the zero state, an output pulse occurs on "0" which presets N. The propagation delays from the Clock's rising and falling edges to the "0" output's rising and falling edges are about equal, making the "0" output pulse approximately equal to that of the Clock pulse. The Inhibit pin may be used to stop pulse counting. When this pin is taken high, decrementing is inhibited. Cascaded, Presettable Divide-By-N Figure 12 shows a three stage cascade application. Taking Reset high loads N. Only the first stage's Reset pin (least significant counter) must be taken high to cause the preset for all stages, but all pins could be tied together, as shown. When the first stage's Reset pin goes high, the "0" output is latched in a high state. Reset must be released while Clock is high and time allowed for Preset Enable to load N into all stages before Clock goes low. When Preset Enable is high and Clock is low, time must be allowed for the zero digits to propagate a Cascade Feedback to the first non-zero stage. Worst case is from the most significant bit (M.S.B.) to the L.S.B., when the L.S.B. is equal to one (i.e. N = 1). After N is loaded, each stage counts down to zero with each rising edge of Clock. When any stage reaches zero and the leading stages (more significant bits) are zero, the "0" output goes high and feeds back to the preceding stage. When all stages are zero, the Preset Enable automatically loads N while the Clock is high and the cycle is renewed. N VDD VSS P0 P1 P2 P3 CF RESET INHIBIT CLOCK PE Q0 Q1 Q2 Q3 "0" BUFFER fin N fin Figure 11. / N Counter LSB N0 N1 N2 N3 P0 P1 P2 P3 fin CLOCK INHIBIT RESET CF "0" PE VSS Q0 Q1 Q2 Q3 N4 N5 N6 N7 P0 P1 P2 P3 CLOCK INHIBIT RESET CF "0" PE VSS Q0 Q1 Q2 Q3 MSB N8 N9 N10 N11 P0 P1 P2 P3 CLOCK INHIBIT RESET Q0 Q1 Q2 Q3 CF "0" PE VDD VSS VDD LOAD N 10 K VSS BUFFER fin N Figure 12. 3 Stages Cascaded MC14522B MC14526B 8 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -B- 1 8 C L -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MOTOROLA CMOS LOGIC DATA MC14522B MC14526B 9 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 -B- 1 8 8X P 0.010 (0.25) M B M 16X D M J TA S 0.010 (0.25) B S F R X 45 _ C -T- 14X DIM A B C D F G J K M P R G K SEATING PLANE M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14522B MC14526B 10 *MC14522B/D* MOTOROLA CMOS LOGIC DATA MC14522B/D |
Price & Availability of MC14522BCL
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |